(1) Field of the Invention
The invention relates to a method for producing a semiconductor device. More specifically, it relates to a method for producing a semiconductor device in which the undesirable etching of an oxide layer on an isolation region of a semiconductor substrate and of an underlayer thereof is prevented during the process of preparing a thick oxide layer on the isolation region.
(2) Description of the Prior Art
In the case of a semiconductor integrated circuit such as a bipolar semiconductor integrated circuit, the technique for surrounding a region with a thick field oxide layer so as to form active or passive elements of the circuit has been developed. Such a semiconductor integrated circuit is illustrated in a schematic sectional view in FIG. 1. In FIG. 1(a), FIG. 1(b), and FIG. 2, the same reference numbers denote the same portions. Reference number 1 indicates a P-type silicon (Si) substrate. Reference number 2 indicates an N.sup.+ -type buried layer. Reference number 3 denotes an N-type silicon epitaxial layer. A P-type base region 4 and N.sup.+ -type emitter region 5 are formed in the epitaxial layer 3. Reference number 6 denotes a P-type isolation region surrounding regions 4 and 5. The P-type isolation region 6 surrounding the element region has an island shape. Reference number 7 denotes an insulating layer formed by a silicon dioxide (SiO.sub.2) layer about 800 nm in thickness. Reference number 7a denotes a silicon dioxide layer about 100.about.150 nm in thickness. Reference number 8 designates a silicon nitride (Si.sub.3 N.sub.4) used as a mask when silicon dioxide is formed by the selective oxidation method. The semiconductor integrated circuit is completed by forming a collector contact region 9, a collector electrode 10, a base electrode 11, an emitter electrode 12, and conductive lines (not shown), respectively.
It is possible to decrease the parasitic capacitance between the epitaxial layer and the conductive lines by forming the above-mentioned insulating layer 7. By using this method, it is possible to selectively oxidize the epitaxial layer 3, keeping the silicon nitride layer 8 on the base region 4, the isolation region 6 and on the collector contact region 9. It is possible to form other elements such as a resistor and a diode by a self-alignment process.
The region formed of a passive element or an active element in the semiconductor integrated circuit, which is prepared by the above-mentioned method, is surrounded by an isolation region having an island shape. Therefore, the conductive lines are formed over the isolation region. As illustrated in FIG. 1(b), when the collector electrode (the conductive line) 10 is formed over the isolation region 6, the silicon dioxide layer 7a is formed on the isolation region 6. However, the thickness of the silicon dioxide layer 7a is thin, namely 100.about.150 nm in thickness. Therefore, the parasitic capacitance C between the conductive line 10 and the isolation region 6 increases so that the switching speed of the thus-produced semiconductor integrated circuit becomes slow. In order to make the parasitic capacitance C small and to make the switching speed fast, it has been attempted to make the silicon dioxide layer 7a on the isolation region 6 thick.
FIG. 2 is another means for making the parasitic capacitance C small. According to the means, a high concentration of P-type impurities (acceptors, e.g., boron) are introduced through the silicon dioxide layer 7 by ion implantation to form a P.sup.+ -type isolation region 6a (FIG. 2). However, this has a drawback in that it is impossible to make the patterning small since the P.sup.+ -type isolation region 6a is not formed by a self-alignment process.
According to the prior art for forming an isolation region by using a self-alignment process, a photoresist layer 13 is coated on the entire surface of the silicon dioxide layer 7, as is illustrated in FIG. 3 (the reference numbers in FIG. 3 designate the same elements as those in FIG. 1), after the first selective oxidation is completed. Then a portion of the photoresist layer 13, corresponding to an isolation region to be formed, is removed. This is followed by introducing impurities through the silicon dioxide layer 7a into the epitaxial layer 3 by ion implantation in order to form the isolation region. In the case of introducing impurities into the epitaxial layer 3, the silicon nitride layer 8 is removed in advance since certain impurities cannot be introduced into the epitaxial layer if the silicon nitride layer is present.
In order to remove the silicon nitride layer 8, a plasma etching method is employed wherein the etchant is, for example, carbon tetrafluoride (CF.sub.4). By using this method, the silicon nitride layer 8 is etched as shown in FIG. 3. One portion of the silicon nitride layer 8 can be etched by employing the above-mentioned etching process. However, one portion of the epitaxial layer 3 below the silicon nitride layer 8 can be undesirably etched, and, in an extreme case, one portion of the epitaxial layer 3 can be hollowed out.